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» Models of Computation for Networks on Chip
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ARVLSI
1999
IEEE
162views VLSI» more  ARVLSI 1999»
14 years 1 months ago
Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking Chip
The ability of animals to select a limited region of sensory space for scrutiny is an important factor in dealing with cluttered or complex sensory environments. Such an attention...
Timothy K. Horiuchi, Ernst Niebur
VLSID
2004
IEEE
170views VLSI» more  VLSID 2004»
14 years 9 months ago
On-chip networks: A scalable, communication-centric embedded system design paradigm
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf
ICS
2011
Tsinghua U.
13 years 7 days ago
Predictive coordination of multiple on-chip resources for chip multiprocessors
Efficient on-chip resource management is crucial for Chip Multiprocessors (CMP) to achieve high resource utilization and enforce system-level performance objectives. Existing mul...
Jian Chen, Lizy Kurian John
CODES
2003
IEEE
14 years 2 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
ICS
2001
Tsinghua U.
14 years 1 months ago
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Ei...