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» Models of Computation for Networks on Chip
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ASPDAC
2009
ACM
135views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Analysis of communication delay bounds for network on chips
—In network-on-chip, computing worst-case delay bound for packet delivery is crucial for designing predictable systems but yet an intractable problem due to complicated resource ...
Yue Qian, Zhonghai Lu, Wenhua Dou
DAC
2006
ACM
14 years 1 months ago
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
A novel routing algorithm, namely dynamic XY (DyXY) routing, is proposed for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at the same time. ...
Ming Li, Qing-An Zeng, Wen-Ben Jone
HPCA
2009
IEEE
14 years 8 months ago
Express Cube Topologies for on-Chip Interconnects
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
EUC
2008
Springer
13 years 9 months ago
Communications via Systems-on-Chips Clustering in Large-Scaled Sensor Networks
In this paper, we have proposed a framework of systems-on-chips clustering in application to complicated sensor networks. The framework can be applied to address the communication ...
Sharon Fan, Jeffrey Fan, Kia Makki, Niki Pissinou