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DAC
2004
ACM
14 years 10 months ago
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
MICCAI
2003
Springer
14 years 10 months ago
Vascular Atlas Formation Using a Vessel-to-Image Affine Registration Method
We have developed a method for forming vascular atlases using vascular distance maps and a novel vascular model-to-image registration method. Our atlas formation process begins wit...
Dini Chillet, Julien Jomier, Derek Cool, Stephen R...
ICCD
2007
IEEE
120views Hardware» more  ICCD 2007»
14 years 6 months ago
Statistical timing analysis using Kernel smoothing
We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary mo...
Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwa...
ICCAD
2005
IEEE
97views Hardware» more  ICCAD 2005»
14 years 6 months ago
DiCER: distributed and cost-effective redundancy for variation tolerance
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, ...
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
14 years 6 months ago
Static statistical timing analysis for latch-based pipeline designs
A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM desi...
Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, San...