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» Multi-Million Gate FPGA Physical Design Challenges
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ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
14 years 25 days ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean
RSP
1999
IEEE
122views Control Systems» more  RSP 1999»
14 years 24 days ago
Incremental Compilation for Logic Emulation
Over the past decade, the steady growth rate of FPGA device capacities has enabled the development of multi-FPGA prototyping environments capable of implementing millions of logic...
Russell Tessier
ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
13 years 6 months ago
A PUF design for secure FPGA-based embedded systems
The concept of having an integrated circuit (IC) generate its own unique digital signature has broad application in areas such as embedded systems security, and IP/IC counterpiracy...
Jason Helge Anderson
TIM
2010
188views Education» more  TIM 2010»
13 years 3 months ago
An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems
Abstract--The most popular representative devices of reconfigurable computing are the Field Programmable Gate Arrays (FPGAs). A promising feature of an FPGA is the ability to reuse...
Kyprianos Papadimitriou, Antonis Anyfantis, Aposto...
BCS
2008
13 years 10 months ago
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation
This paper describes our approaches to raise the level of abstraction at which hardware suitable for accelerating computationally-intensive applications can be specified. Field-Pr...
Qiang Liu, George A. Constantinides, Konstantinos ...