54 search results - page 1 / 11 » Multi-level logic optimization for low power using local log... |
ICCAD
1996
IEEE
14 years 21 days ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
ARVLSI
1995
IEEE
14 years 3 days ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
DAC
1997
ACM
14 years 3 days ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
ICCAD
1997
IEEE
14 years 22 days ago
1997
IEEE
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...