377 search results - page 39 / 76 » Multiple Instruction Stream Processor |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...
ISCA
1998
IEEE
13 years 12 months ago
1998
IEEE
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly chan...
ARITH
2007
IEEE
14 years 2 months ago
2007
IEEE
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...