377 search results - page 6 / 76 » Multiple Instruction Stream Processor |
IJAIT
2008
13 years 7 months ago
2008
Instruction scheduling is one of the most important steps for improving the performance of object code produced by a compiler. A fundamental problem that arises in instruction sch...
ISCA
2000
IEEE
14 years 1 days ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
— A flexible transport stream processor for DTV which is also designed under cost-effective consideration is proposed in this paper. A RISC micro-controller is allocated as the ...
MICRO
2002
IEEE
14 years 17 days ago
2002
IEEE
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...
JSA
2007
13 years 7 months ago
2007
Trivial instructions are those instructions whose output can be determined without performing the actual computation. This is due to the fact that for these instructions the outpu...