Sciweavers

983 search results - page 171 / 197
» Negative-Weight Cycle Algorithms
Sort
View
ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
14 years 6 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
SASO
2008
IEEE
14 years 4 months ago
Towards Desynchronization of Multi-hop Topologies
In this paper we study desynchronization, a closelyrelated primitive to graph coloring. A valid graph coloring is an assignment of colors to nodes such that no node’s color is t...
Julius Degesys, Radhika Nagpal
ISQED
2007
IEEE
127views Hardware» more  ISQED 2007»
14 years 4 months ago
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Ch...
DATE
2010
IEEE
190views Hardware» more  DATE 2010»
14 years 2 months ago
Ultra-high throughput string matching for Deep Packet Inspection
Deep Packet Inspection (DPI) involves searching a packet's header and payload against thousands of rules to detect possible attacks. The increase in Internet usage and growing...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
SIGGRAPH
1998
ACM
14 years 2 months ago
Visibility Sorting and Compositing Without Splitting for Image Layer Decompositions
We present an efficient algorithm for visibility sorting a set of moving geometric objects into a sequence of image layers which are composited to produce the final image. Inste...
John M. Snyder, Jed Lengyel