278 search results - page 10 / 56 » Network Topology Design to Optimize Link and Switching Costs |
ISCA
2010
IEEE
14 years 15 days ago
2010
IEEE
Numerous studies have shown that datacenter computers rarely operate at full utilization, leading to a number of proposals for creating servers that are energy proportional with r...
GECCO
2010
Springer
14 years 6 days ago
2010
Springer
The Spidergon interconnection network has become popular recently in multiprocessor systems on chips. To the best of our knowledge, algorithms for collective communications (CC) h...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
QOSIP
2005
Springer
14 years 27 days ago
2005
Springer
Abstract. The topological design of distributed packet switched networks consists of finding a topology that minimizes the communication costs by taking into account a certain num...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...