Sciweavers

998 search results - page 85 / 200
» Networked Embedded Systems: A Quantitative Performance Compa...
Sort
View
102
Voted
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
15 years 9 months ago
Networks on chips for high-end consumer-electronics TV system architectures
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
Frits Steenhof, Harry Duque, Björn Nilsson, K...
IROS
2006
IEEE
111views Robotics» more  IROS 2006»
15 years 9 months ago
A Delay-tolerant, Potential field-based, Network Implementation of an Integrated Navigation System
Abstract—Network controllers (NCs) are devices that are capable of converting dynamic, spatially extended, and functionally specialized modules into a taskable goal-oriented grou...
Rachana Ashok Gupta, Ahmad A. Masoud, Mo-Yuen Chow
108
Voted
IPPS
1995
IEEE
15 years 7 months ago
The RACE network architecture
The RACE R parallel computer system provides a highperformance parallel interconnection network at low cost. This paper describes the architecture and implementation of the RACE ...
Bradley C. Kuszmaul
125
Voted
ICCD
2004
IEEE
123views Hardware» more  ICCD 2004»
16 years 16 days ago
Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures
The work presents a modeling and analysis framework for heterogeneous industrial networks architectures which is based on a tight integration of a network simulator with embedded ...
Franco Fummi, Stefano Martini, Marco Monguzzi, Gio...
119
Voted
SBCCI
2004
ACM
117views VLSI» more  SBCCI 2004»
15 years 9 months ago
Reducing test time with processor reuse in network-on-chip based systems
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Alexandre M. Amory, Érika F. Cota, Marcelo ...