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» New methods and coverage metrics for functional verification
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FMCAD
1998
Springer
13 years 11 months ago
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
Sergey Berezin, Armin Biere, Edmund M. Clarke, Yun...
DAC
2003
ACM
14 years 8 months ago
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on enco...
Sanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Br...
DAC
2004
ACM
13 years 11 months ago
Communication-efficient hardware acceleration for fast functional simulation
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong...
TC
1998
13 years 7 months ago
Abstraction Techniques for Validation Coverage Analysis and Test Generation
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Ho...
ICCAD
1996
IEEE
93views Hardware» more  ICCAD 1996»
13 years 11 months ago
VERILAT: verification using logic augmentation and transformations
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatter...