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» NoC-Based FPGA: Architecture and Routing
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FPL
2003
Springer
109views Hardware» more  FPL 2003»
14 years 1 months ago
Globally Asynchronous Locally Synchronous FPGA Architectures
Abstract. Globally Asynchronous Locally Synchronous (GALS) Systems have provoked renewed interest over recent years as they have the potential to combine the benefits of asynchron...
Andrew Royal, Peter Y. K. Cheung
FPGA
2003
ACM
138views FPGA» more  FPGA 2003»
14 years 1 months ago
Automatic transistor and physical design of FPGA tiles from an architectural specification
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywher...
Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron E...
FPGA
2006
ACM
125views FPGA» more  FPGA 2006»
14 years 7 days ago
Armada: timing-driven pipeline-aware routing for FPGAs
While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups ha...
Kenneth Eguro, Scott Hauck
DAC
1995
ACM
14 years 4 days ago
Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing
We propose a novel optimization scheme that can improve the routing by reducing a newly observed router decaying effect. A pair of greedy-grow algorithms, each emphasizing a diffe...
Yu-Liang Wu, Malgorzata Marek-Sadowska
FPGA
1999
ACM
115views FPGA» more  FPGA 1999»
14 years 26 days ago
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
Alexander Marquardt, Vaughn Betz, Jonathan Rose