152 search results - page 8 / 31 » Noise considerations in circuit optimization |
DAC
1999
ACM
14 years 8 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
ISVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circ...
TASLP
2008
13 years 7 months ago
2008
Noise reduction, which aims at estimating a clean speech from noisy observations, has attracted a considerable amount of research and engineering attention over the past few decade...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...