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» Noise-tolerant dynamic circuit design
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ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
12 years 4 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 12 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
DATE
2003
IEEE
100views Hardware» more  DATE 2003»
14 years 1 months ago
Dynamic Tool Integration in Heterogeneous Computer Networks
Tool installation and automation of administrative tasks in heterogeneous computer networks becomes of increasing importance with the availability of complex heterogeneous compute...
Wolfgang Müller 0003, Tim Schattkowsky, Heinz...
DAC
2005
ACM
14 years 9 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
DAC
2006
ACM
14 years 9 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang