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» Noise-tolerant dynamic circuit design
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DAC
2009
ACM
14 years 10 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
CF
2005
ACM
13 years 11 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
14 years 3 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
ICRA
2010
IEEE
151views Robotics» more  ICRA 2010»
13 years 7 months ago
A robust, low-cost and low-noise artificial skin for human-friendly robots
As robots and humans move towards sharing the same environment, the need for safety in robotic systems is of growing importance. Towards this goal of human-friendly robotics, a rob...
John Ulmen, Mark R. Cutkosky
ISPD
2010
ACM
163views Hardware» more  ISPD 2010»
14 years 4 months ago
A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems
Thermal/power issues have become increasingly important with more and more transistors being put on a single chip. Many dynamic thermal/power management techniques have been propo...
Yufu Zhang, Bing Shi, Ankur Srivastava