339 search results - page 62 / 68 » Noise-tolerant dynamic circuit design |
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
—In [1], we have shown that it is feasible to design filters with arbitrary waveform responses and therefore we propose an ultra-wideband pulse generator incorporating a filter w...
ISCA
2003
IEEE
14 years 19 days ago
2003
IEEE
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...
ISCA
2002
IEEE
14 years 8 days ago
2002
IEEE
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...