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    » Noise-tolerant dynamic circuit design
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    ET
    2007
    111views more  ET 2007»
    Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware
    13 years 7 months ago
    Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware
    Download  lyle.smu.edu
    This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a...
    Fatih Kocan, Daniel G. Saab
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    ASPDAC
    2008
    ACM
    103views Hardware» more  ASPDAC 2008»
    Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification
    13 years 9 months ago
    Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification
    Download  www.cecs.uci.edu
    This paper presents an all digital measurement circuit called "gated oscillator" for capturing waveforms of dynamic power supply noise. The gated oscillator is constructe...
    Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoy...
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    DAC
    2010
    ACM
    156views Computer Architecture» more  DAC 2010»
    Circuit modeling for practical many-core architecture design exploration
    13 years 11 months ago
    Circuit modeling for practical many-core architecture design exploration
    Download  www.ece.ucdavis.edu
    Current tools for computer architecture design lack standard support for multi- and many-core development. We propose using circuit models to describe the multiple processor archi...
    Dean Truong, Bevan M. Baas
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    ISQED
    2007
    IEEE
    197views Hardware» more  ISQED 2007»
    A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
    14 years 1 months ago
    A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
    Download  www.c.csce.kyushu-u.ac.jp
    The deep submicron (DSM) semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions sho...
    Toshinori Sato, Yuji Kunitake
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    DAC
    2007
    ACM
    131views Computer Architecture» more  DAC 2007»
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    14 years 8 months ago
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    Download  cobweb.ecn.purdue.edu
    This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
    Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
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