980 search results - page 12 / 196 » Novel Test Pattern Generators for Pseudo-Exhaustive Testing |
ET
2002
13 years 9 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compat...
EURODAC
1994
IEEE
14 years 1 months ago
1994
IEEE
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
VTS
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...