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» Novel Test Pattern Generators for Pseudo-Exhaustive Testing
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VLSID
2010
IEEE
155views VLSI» more  VLSID 2010»
13 years 7 months ago
Synchronized Generation of Directed Tests Using Satisfiability Solving
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
Xiaoke Qin, Mingsong Chen, Prabhat Mishra
ICCAD
1995
IEEE
120views Hardware» more  ICCAD 1995»
14 years 22 days ago
Pattern generation for a deterministic BIST scheme
Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic ...
Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, ...
VTS
2008
IEEE
136views Hardware» more  VTS 2008»
14 years 3 months ago
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Te...
ESOP
2012
Springer
12 years 4 months ago
Generate, Test, and Aggregate - A Calculation-based Framework for Systematic Parallel Programming with MapReduce
Abstract. MapReduce, being inspired by the map and reduce primitives available in many functional languages, is the de facto standard for large scale data-intensive parallel progra...
Kento Emoto, Sebastian Fischer, Zhenjiang Hu
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 3 months ago
Concurrent core test for SOC using shared test set and scan chain disable
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
Gang Zeng, Hideo Ito