Sciweavers

980 search results - page 33 / 196
» Novel Test Pattern Generators for Pseudo-Exhaustive Testing
Sort
View
MTDT
2000
IEEE
129views Hardware» more  MTDT 2000»
14 years 1 months ago
Using GLFSRs for Pseudo-Random Memory BIST
In this work, we present the application of Generalized Linear Feedback Shift Registers (GLFSRs) for generation of patterns for pseudo-random memory Built-In SelfTest (BIST). Rece...
Michael Redeker, Markus Rudack, Thomas Lobbe, Dirk...
DAC
1996
ACM
14 years 1 months ago
Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths
The testability of basic DSP datapath structures using pseudorandom built-in self-test techniques is examined. The addition of variance mismatched signals is identified as a testi...
Laurence Goodby, Alex Orailoglu
VTS
2007
IEEE
129views Hardware» more  VTS 2007»
14 years 3 months ago
Supply Voltage Noise Aware ATPG for Transition Delay Faults
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
VTS
1999
IEEE
106views Hardware» more  VTS 1999»
14 years 1 months ago
RT-level TPG Exploiting High-Level Synthesis Information
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto