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» Novel Test Pattern Generators for Pseudo-Exhaustive Testing
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ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Constraint extraction for pseudo-functional scan-based delay testing
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...
Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Chen...
ASPDAC
2009
ACM
262views Hardware» more  ASPDAC 2009»
14 years 3 months ago
Fault modeling and testing of retention flip-flops in low power designs
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...
RSP
1998
IEEE
126views Control Systems» more  RSP 1998»
14 years 1 months ago
Testing Prototypes Validity to Enhance Code Reuse
The complexity of distributed systems is a problem when designers want to evaluate their safety and liveness. Often, they are built by integration of existing components with newl...
Didier Buchs, A. Diagne, Fabrice Kordon
ICCAD
2000
IEEE
100views Hardware» more  ICCAD 2000»
14 years 1 months ago
Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog Circuits
In this paper, we propose a novel fault-oriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuit-underte...
Sudip Chakrabarti, Abhijit Chatterjee
VTS
1998
IEEE
97views Hardware» more  VTS 1998»
14 years 1 months ago
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Mat...