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» Novel Test Pattern Generators for Pseudo-Exhaustive Testing
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ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
14 years 1 months ago
Deterministic Test Pattern Generation Techniques for Sequential Circuits
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
Ilker Hamzaoglu, Janak H. Patel
ATS
2009
IEEE
132views Hardware» more  ATS 2009»
14 years 4 months ago
On Improving Diagnostic Test Generation for Scan Chain Failures
In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
14 years 2 months ago
Effective TARO Pattern Generation
TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to i...
Intaik Park, Ahmad A. Al-Yamani, Edward J. McClusk...
DAC
2006
ACM
14 years 10 months ago
Timing-based delay test for screening small delay defects
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
TAP
2010
Springer
102views Hardware» more  TAP 2010»
14 years 2 months ago
Generating High-Quality Tests for Boolean Circuits by Treating Tests as Proof Encoding
Abstract. We consider the problem of test generation for Boolean combinational circuits. We use a novel approach based on the idea of treating tests as a proof encoding rather than...
Eugene Goldberg, Panagiotis Manolios