372 search results - page 10 / 75 » On Fault Testing for Reversible Circuits |
DAC
1994
ACM
14 years 20 days ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
We study the undetectable faults in partial scan circuits under a test application scheme referred to as transparent-scan. The transparent-scan approach allows very aggressive tes...
CORR
2010
Springer
13 years 8 months ago
2010
Springer
In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circ...
DSD
2007
IEEE
14 years 2 months ago
2007
IEEE
Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability id...
DSD
2005
IEEE
14 years 2 months ago
2005
IEEE
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...