This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...