372 search results - page 18 / 75 » On Fault Testing for Reversible Circuits |
EURODAC
1994
IEEE
14 years 22 days ago
1994
IEEE
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
ATS
1996
IEEE
14 years 23 days ago
1996
IEEE
A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from t...
ET
1998
13 years 8 months ago
1998
This paper explores the design of efficient test sets and test-pattern generators for online BIST. The target applications are high-performance, scalable datapath circuits for whi...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
The importance of testing approaches that exploit error tolerance to improve yield has previously been established. Error rate, defined as the percentage of vectors for which the...