372 search results - page 3 / 75 » On Fault Testing for Reversible Circuits |
IOLTS
2007
IEEE
14 years 1 months ago
2007
IEEE
Security of cryptographic circuits is a major concern. Fault attacks are a mean to obtain critical information with the use of physical disturbance and cryptanalysis. We propose a...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
JUCS
2007
13 years 7 months ago
2007
: This paper describes a method of using Petri net P-invariants in system diagnosis. To model this process a net oriented fault classification is presented. Hence, the considered d...