372 search results - page 4 / 75 » On Fault Testing for Reversible Circuits |
CORR
2010
Springer
13 years 2 months ago
2010
Springer
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its correspon...
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT, including fault ordering, state predict...
JISE
2000
13 years 7 months ago
2000
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
VTS
2003
IEEE
14 years 22 days ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...