372 search results - page 9 / 75 » On Fault Testing for Reversible Circuits |
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
A unified approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the set...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
DFT
2002
IEEE
14 years 1 months ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
ICCAD
1990
IEEE
14 years 19 days ago
1990
IEEE
Partial detectability profiles are formed by randomly sampling each fault's detectability and are used in estimating the fault coverage of random input test vectors on combin...