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CODES
2005
IEEE
14 years 3 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
CODES
2005
IEEE
14 years 3 months ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...
ICRA
2005
IEEE
168views Robotics» more  ICRA 2005»
14 years 3 months ago
Control of Scalable Wet SMA Actuator Arrays
- This paper presents a new control method to drive an array of wet Shape Memory Alloy actuators utilizing a Matrix Manifold and Valve system (MMV). The MMV architecture allows a v...
L. Flemming, Stephen A. Mascaro
INFOCOM
2005
IEEE
14 years 3 months ago
Fairness in MIMD congestion control algorithms
The Mulitplicative Increase Multiplicative Decrease (MIMD) congestion control algorithm in the form of Scalable TCP has been proposed for high speed networks. We study fairness amo...
Eitan Altman, Konstantin Avrachenkov, B. J. Prabhu
ISPAN
2005
IEEE
14 years 3 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
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