216 search results - page 6 / 44 » On High-Bandwidth Data Cache Design for Multi-Issue Processo... |
EUROPAR
2008
Springer
13 years 9 months ago
2008
Springer
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity i...
ISCA
2003
IEEE
14 years 1 months ago
2003
IEEE
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
PATMOS
2010
Springer
13 years 5 months ago
2010
Springer
In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power con...