82 search results - page 5 / 17 » On Structural vs. Functional Testing for Delay Faults |
ITC
1996
IEEE
14 years 28 days ago
1996
IEEE
This paper describes test generation for delay faults caused by global process disturbances. The structural and spatial correlation between path delays is used to reduce the numbe...
ATS
2003
IEEE
14 years 2 months ago
2003
IEEE
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
VTS
1996
IEEE
14 years 28 days ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...