1529 search results - page 173 / 306 » On Timing Analysis of Combinational Circuits |
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
On public communication networks such as the Internet, data confidentiality can be provided by symmetric-key ciphers. One of the most common operations used in symmetric-key ciphe...
ISQED
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— To achieve small delay and low crosstalk for multiple signal nets with capacitive and inductive coupling, we propose in this paper a novel interconnect structure, stagg...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
ITC
2000
IEEE
14 years 16 days ago
2000
IEEE
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
IFIP
1999
Springer
14 years 13 days ago
1999
Springer
In this paper we describe Frontier, an FPGA placement system that uses design macro-blocks in conjuction with a series of placement algorithms to achieve highly-routable and high-...