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» On Timing Analysis of Combinational Circuits
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CODES
2005
IEEE
14 years 1 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
ICCAD
1999
IEEE
88views Hardware» more  ICCAD 1999»
14 years 9 days ago
Performance optimization under rise and fall parameters
Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performan...
Rajeev Murgai
ICCAD
1999
IEEE
148views Hardware» more  ICCAD 1999»
14 years 9 days ago
SAT based ATPG using fast justification and propagation in the implication graph
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
Paul Tafertshofer, Andreas Ganz
DAC
1997
ACM
14 years 6 days ago
Electronic Component Information Exchange (ECIX)
A number of industry trends are shaping the requirements for IC and electronic equipment design. The density and complexity of circuit technologies have increased to a point where...
Donald R. Cottrell
GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
13 years 12 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos