180 search results - page 12 / 36 » On digit-recurrence division implementations for field progr... |
FPL
2007
Springer
14 years 1 months ago
2007
Springer
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arr...
FCCM
2009
IEEE
13 years 11 months ago
2009
IEEE
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
With rapid advances in VLSI technology, Field Programmable Gate Arrays (FPGAs) are receiving the attention of the Parallel and High Performance Computing community. In this paper,...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents a new family of architectures for multi-cycle area-efficient evaluation of elementary and composite functions, and an exploration of the design tradeoffs for i...
INTEGRATION
2008
13 years 6 months ago
2008
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...