2658 search results - page 112 / 532 » On efficient balanced codes |
DSD
2007
IEEE
14 years 4 months ago
2007
IEEE
In this paper, we present an efficient hardware architecture for real-time implementation of quarter-pixel accurate variable block size motion estimation for H.264 / MPEG4 Part 10...
ICN
2005
Springer
14 years 3 months ago
2005
Springer
: Power Conservation is one of the most important challenges in wireless sensor networks. In this paper, we present two minimum-energy routing algorithms. Our main goal is to reduc...
ISCA
1999
IEEE
14 years 1 months ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
HPCA
2006
IEEE
14 years 10 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
IESS
2007
Springer
14 years 3 months ago
2007
Springer
To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation...