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VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
14 years 10 months ago
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
Rahul Jain, Preeti Ranjan Panda
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
14 years 6 months ago
Delay and Area Efficient First-level Cache Soft Error Detection and Correction
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
Karl Mohr, Lawrence Clark
ICCD
2003
IEEE
140views Hardware» more  ICCD 2003»
14 years 6 months ago
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems
NAND flash memory has become an indispensable component in embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cos,t and high d...
Chanik Park, Jaeyu Seo, Dongyoung Seo, Shinhan Kim...
ICMCS
2006
IEEE
98views Multimedia» more  ICMCS 2006»
14 years 3 months ago
Unequal Iterative Decoding for Power Efficient Video Transmission
We present an unequal iterative decoding (UID) approach for minimization of the receiver power consumption subject to a given quality of service, by exploiting data partitioning a...
Yongfang Wang, Songyu Yu, Xiaokang Yang
ASPDAC
1998
ACM
160views Hardware» more  ASPDAC 1998»
14 years 1 months ago
Synthesis of Power Efficient Systems-on-Silicon
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...
Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...