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» On modeling top-down VLSI design
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GLVLSI
2008
IEEE
157views VLSI» more  GLVLSI 2008»
14 years 2 months ago
Coverage-driven automatic test generation for uml activity diagrams
Due to the increasing complexity of today’s embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded...
Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita
GLVLSI
2009
IEEE
154views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Design of a maximum-likelihood detector for cooperative communications in intersymbol interference channels
Recently, cooperative communication has attracted a lot of attention for its potential to increase spatial diversity. However, limited attention has been paid to the physical laye...
Yanjie Peng, Andrew G. Klein, Xinming Huang
GLVLSI
2010
IEEE
310views VLSI» more  GLVLSI 2010»
14 years 10 days ago
Graphene tunneling FET and its applications in low-power circuit design
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Moh...
GLVLSI
2006
IEEE
185views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Application of fast SOCP based statistical sizing in the microprocessor design flow
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
Murari Mani, Mahesh Sharma, Michael Orshansky
ISSS
2002
IEEE
130views Hardware» more  ISSS 2002»
14 years 15 days ago
System-Level Modeling of a Network Switch SoC
We present the modeling of the high-level design of a next generation network switch from the perspective of a ComputerAided Design (CAD) team within the larger context of a desig...
Andrew S. Cassidy, Christopher P. Andrews, Donald ...