305 search results - page 18 / 61 » On modeling top-down VLSI design |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Abstract - The deep sub-micron regime has broughtup several manufacturing issues which impact circuit-performance and design. One such issue is flaring of transistors which causes ...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Loical defect diagnosis is a critical yet challenging process in VLSI manufacturing. It involves the identification of the defect spots in a logic IC that fails testing. In the la...
ISVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
We present a methodology and algorithms for automatic refinement from a given design specification to an architecture model based on decisions in architecture exploration. An arch...