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» On modeling top-down VLSI design
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VLSID
2000
IEEE
102views VLSI» more  VLSID 2000»
13 years 12 months ago
Inductance Characterization of Small Interconnects Using Test-Signal Method
The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in highdensity IC’s by using a test signa...
Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal
VLSI
2010
Springer
13 years 2 months ago
SESAM extension for fast MPSoC architectural exploration and dynamic streaming applications
Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. To overcome these...
Nicolas Ventroux, Tanguy Sassolas, Raphael David, ...
SLIP
2005
ACM
14 years 1 months ago
Congestion prediction in early stages
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
Chiu-Wing Sham, Evangeline F. Y. Young
GLVLSI
2008
IEEE
137views VLSI» more  GLVLSI 2008»
14 years 1 months ago
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...
Ann Gordon-Ross, Jeremy Lau, Brad Calder
ISVLSI
2008
IEEE
142views VLSI» more  ISVLSI 2008»
14 years 1 months ago
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing
In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation e...
Venkataraman Mahalingam, Nagarajan Ranganathan