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» On modeling top-down VLSI design
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SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
14 years 1 months ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
DAC
2002
ACM
14 years 8 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
ISLPED
2003
ACM
113views Hardware» more  ISLPED 2003»
14 years 22 days ago
Reducing power density through activity migration
Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Exc...
Seongmoo Heo, Kenneth C. Barr, Krste Asanovic
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
13 years 11 months ago
Repeater insertion in RLC lines for minimum propagation delay
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
14 years 23 days ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...