140 search results - page 6 / 28 » On multiple-voltage high-level synthesis using algorithmic t... |
ICCAD
1997
IEEE
14 years 1 months ago
1997
IEEE
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
DAC
2012
ACM
11 years 11 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
FPL
2009
Springer
14 years 28 days ago
2009
Springer
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
— This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by...