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» On test coverage of path delay faults
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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 7 months ago
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Pun...
VLSID
1996
IEEE
110views VLSI» more  VLSID 1996»
14 years 3 months ago
On test coverage of path delay faults
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
ITC
2003
IEEE
120views Hardware» more  ITC 2003»
14 years 4 months ago
High Quality ATPG for Delay Defects
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
Puneet Gupta, Michael S. Hsiao
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
14 years 3 months ago
Exact Grading of Multiple Path Delay Faults
The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulate...
Saravanan Padmanaban, Spyros Tragoudas
VTS
2000
IEEE
94views Hardware» more  VTS 2000»
14 years 3 months ago
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng