Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Pun...
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulate...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...