166 search results - page 21 / 34 » On testing delay faults in macro-based combinational circuit... |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
VTS
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
DATE
1999
IEEE
14 years 3 days ago
1999
IEEE
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
ICCAD
1997
IEEE
14 years 7 hour ago
1997
IEEE
A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems ...
DATE
1999
IEEE
14 years 3 days ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...