166 search results - page 25 / 34 » On testing delay faults in macro-based combinational circuit... |
ITC
1998
IEEE
14 years 1 days ago
1998
IEEE
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
DSD
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
VLSID
1993
IEEE
13 years 12 months ago
1993
IEEE
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
—Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integ...