166 search results - page 5 / 34 » On testing delay faults in macro-based combinational circuit... |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
ICCAD
1991
IEEE
13 years 11 months ago
1991
IEEE
This paper presents an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The algorithm is able to ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Abstract— Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored...
DAC
1994
ACM
13 years 12 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...