166 search results - page 8 / 34 » On testing delay faults in macro-based combinational circuit... |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
ICCAD
1998
IEEE
14 years 1 days ago
1998
IEEE
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
ITC
2002
IEEE
14 years 21 days ago
2002
IEEE
ETS
2006
IEEE
14 years 1 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
DFT
1998
IEEE
14 years 1 days ago
1998
IEEE
In the presence of multiple delay faults, automated diagnostic procedures that make a single fault assumption may give an incorrect diagnosis. In this paper, a systematic approach...