Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
Emre Salman, Renatas Jakushokas, Eby G. Friedman, ...
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
From a computational perspective, there is a close connection between various probabilistic reasoning tasks and the problem of counting or sampling satisfying assignments of a pro...
- A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and ...