1795 search results - page 76 / 359 » On the Complexity of Circuit Satisfiability |
ASYNC
2002
IEEE
14 years 1 months ago
2002
IEEE
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
GLVLSI
2009
IEEE
14 years 19 days ago
2009
IEEE
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
AAAI
2004
13 years 10 months ago
2004
From a computational perspective, there is a close connection between various probabilistic reasoning tasks and the problem of counting or sampling satisfying assignments of a pro...
ICCD
2008
IEEE
14 years 5 months ago
2008
IEEE
- A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and ...