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IEEEPACT
2007
IEEE
14 years 3 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
INFOCOM
2007
IEEE
14 years 3 months ago
Separability and Topology Control of Quasi Unit Disk Graphs
— A deep understanding of the structural properties of wireless networks is critical for evaluating the performance of network protocols and improving their designs. Many protoco...
Jianer Chen, Anxiao Jiang, Iyad A. Kanj, Ge Xia, F...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
14 years 3 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
14 years 3 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
MICRO
2007
IEEE
79views Hardware» more  MICRO 2007»
14 years 3 months ago
Time Interpolation: So Many Metrics, So Few Registers
The performance of computer systems varies over the course of their execution. A system may perform well during some parts of its execution and poorly during others. To understand...
Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswir...
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