115 search results - page 12 / 23 » On the Design of IEEE Compliant Floating Point Units |
ARITH
2009
IEEE
13 years 11 months ago
2009
IEEE
This paper deals with the design and implementation of low latency software for binary floating-point division with correct rounding to nearest. The approach we present here targe...
ARITH
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) logarithmic converter based on the digit-recurrence algorithm. The converter can calc...
ISPAN
2005
IEEE
14 years 1 months ago
2005
IEEE
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated...
TC
2010
13 years 6 months ago
2010
—Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a ne...
DATE
1999
IEEE
14 years 1 days ago
1999
IEEE
Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The p...