372 search results - page 16 / 75 » On the Fault Testing for Reversible Circuits |
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
We investigate a characterization of hard-to-detect bridging faults. For circuits with large numbers of lines (or nodes), this characterization can be used to select target faults...
DFT
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...
ETS
2009
IEEE
2009
IEEE
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
13 years 6 months ago
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...